The definition of a gate line over non-planar surfaces, and in particular forming a surrounding gate around a cylindrical surface, such as a nanowire channel, is challenging. In this regard, the gate definition process has several important requirements. First, the gate should have the same length (i.e., distance between source and drain regions) as it wraps around the cylindrical channel surface. To achieve uniform gate length, the gate needs to be patterned having straight sidewalls. For example, if the gate sidewalls are sloped then the top surface of the cylindrical channel would be covered by a shorter portion of the gate material as compared with the coverage of the bottom surface of the cylindrical channel. See, for example, S. Bangsaruntip et al., “High Performance and Highly Uniform Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling,” IEDM, Baltimore, Md. (2009) (hereinafter “Bansaruntip”) (FIG. 6(b) illustrates a gate with sloped sidewalls). Second, any gate conductor material outside of the channel region (including underneath the nanowire channels) has to be removed. This requirement is difficult to achieve with conventionally employed directional etching methods such as reactive ion etching (RIE) since the nanowires mask the etching of the gate conductor material underneath the nanowires. Third, the integrity of the nanowires outside of the gate region needs to be preserved during the patterning of the gate.
With regard to the third requirement, suspended nanowires are typically needed to fabricate a surrounding gate. The nanowires can be suspended, for example, by undercutting an insulator (such as a buried oxide (BOX)) below the nanowires. The gate material has to be deposited under the nanowires in order to obtain a surrounding gate. This suggests that to form a gate line one needs to etch past the nanowire and continue etching until the BOX is reached. Thus, during gate definition the etching has to continue even after gate dielectric on top of the nanowires is exposed (to clear the gate material around the nanowires) which can lead to severance of the nanowires due to a finite etch rate of the gate dielectric. Additionally, the gate dielectric is typically made very thin. As a result if the gate dielectric is removed, the nanowire body will be exposed and will also etch. If the etching is stopped once the gate dielectric is exposed, the definition of the gate line all around the nanowire would not be completed. By comparison, with a planar device the etching process can be stopped once the gate conductor material is cleared from the planar surfaces outside of the gate region since the definition of the gate line is complete at this point.
Current gate etching processes produce non-uniform gate lines over the nanowire surfaces, and can lead to severance of small diameter nanowires. Maintaining the integrity of the nanowires during RIE is even more challenging when the gate line is formed over a stacked (multi-layer) nanowire array. The top nanowires are exposed to continuous bombardment of ions until the bottom nanowires in the stack are cleared from the gate conductor material.
Therefore, techniques for forming a gate line with straight sidewalls, while maintaining the integrity of nanowires outside the gate line region, would be desirable.